• mariusafa@lemmy.sdf.org
    link
    fedilink
    English
    arrow-up
    0
    ·
    6 months ago

    Why Occident doesn’t do the same ?? RISC-V is a libre hardware movement created and moved by many Occident Universities and yet we have few RISC-V in the market.

    Are we too much stagnated with corporation products or what?

    • Railcar8095@lemm.ee
      link
      fedilink
      English
      arrow-up
      0
      ·
      6 months ago

      Because as a business, it doesn’t make sense in occident. They will be much worse in price to performance, and probably forget to run windows or other software.

      From a business sense, it mostly makes sense of you think being dependent on “traditional” is a risk in a way or another.

    • _NoName_@lemmy.ml
      link
      fedilink
      English
      arrow-up
      0
      ·
      6 months ago

      There is often a very limited market for underperforming hardware, which is how RISC-V chips will be starting out. There is a large amount of accumulated knowledge about, and workflow to accommodate, already established ISAs.

      Due to most companies being publicly traded, taking risks is much less common, since a drop in profits could see a massive portion of the company’s funds get pulled, or more likely the CEO being yanked by the board. So they play it safe and choose already established architectures.

  • whaleross@lemmy.world
    link
    fedilink
    English
    arrow-up
    0
    ·
    6 months ago

    Performing sufficiently for cheap production cost, they’d be a low RISC high reward investment.

  • Addv4@lemmy.world
    link
    fedilink
    English
    arrow-up
    0
    ·
    6 months ago

    No gonna lie, this is really cool. While the efficiency isn’t great, for a first attempt these are surprisingly decent specs for what is effectively a mobile cpu. Their server level ones also are pretty decent, and while they aren’t really a match for the newest zen architecture, they are also a first attempt on an architecture that isn’t x86 or arm (some mix of risc v and mips).